Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!ucsd!ucbvax!sprite.berkeley.edu!tve From: tve@sprite.berkeley.edu (Thorsten von Eicken) Newsgroups: comp.arch Subject: Re: RISC hard to program? (was: Moto's data predicts...) Message-ID: <37570@ucbvax.BERKELEY.EDU> Date: 15 Jul 90 00:54:25 GMT References: <40088@mips.mips.COM> <2162@opus.cs.mcgill.ca> <1990Jul13.071511.22250@Neon.Stanford.EDU> Sender: usenet@ucbvax.BERKELEY.EDU Reply-To: tve@sprite.berkeley.edu (Thorsten von Eicken) Organization: University of California, Berkeley Lines: 15 In article wsd@cs.brown.edu (Wm. Scott `Spot' Draves) writes: >In article <1990Jul13.071511.22250@Neon.Stanford.EDU> kaufman@Neon.Stanford.EDU (Marc T. Kaufman) writes: >> SPARC requires fullword alignment for 32-bit operands and DOUBLEword >> alignment (e.g. 8-bytes) for 64-bit operands, in memory. >Are you sure? I think doubles can be loaded from 4 byte boundaries. >Witness the following code, which runs fine on this SS1: >[sample C code removed] This really depends on how doubles get loaded/stored. If the compiler uses the load-double instruction, the data better be aligned on a double (8 byte) boundary. If two load-word instructions are used, word alignment is fine. I haven't figured out when compilers use which instructions, but I have seen both. --- Thorsten von Eicken (tve@sprite.berkeley.edu)