Xref: utzoo comp.arch:17154 comp.compilers:1052 Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!usc!samsung!uunet!lotus!esegue!compilers-sender From: aglew@dwarfs.crhc.uiuc.edu (Andy Glew) Newsgroups: comp.arch,comp.compilers Subject: Re: Register Allocation and Aliasing Keywords: optimize, code Message-ID: <1990Jul16.150553.23357@esegue.segue.boston.ma.us> Date: 16 Jul 90 15:05:53 GMT References: <1990Jul06.194618.4957@esegue.segue.boston.ma.us> <1990Jul15.205606.19343@esegue.segue.boston.ma.us> Sender: compilers-sender@esegue.segue.boston.ma.us Reply-To: aglew@dwarfs.crhc.uiuc.edu (Andy Glew) Followup-To: comp.arch,comp.compilers Organization: University of Illinois, Computer Systems Group Lines: 36 Approved: compilers@esegue.segue.boston.ma.us In-Reply-To: mike@vlsivie.at's message of 15 Jul 90 20:56:06 GMT >IT EVEN HAS A NAME: it's called ``cache memory''. Access times are short >and if integrated on the chip can be as fast as a register access. As I am sure Mr. Gschwind knows, cache implemented on-chip is not as fast as register access, chiefly because cache is seldom multiported, as well as for other reasons such as loading, and the number of addresses that can be specified in an instruction. If you will, we are talking about the space formed by the cross-product of the following parameters: ADDRESSING = by memory address and/or by register number MULTIPORTING = 1r/w .. 2r/1w ... SIZE/SPEED = large/slow .. small/fast The standard configurations are CACHE = addressed by memory address (associatively) single-ported large/slow (at least wrt. registers) REGISTER = addressed by number multiported small/fast What I was asking about, and what Hank Dietz et al, and others, have explored, is whether there are other configurations between these two extremes that might be useful. -- Andy Glew, aglew@uiuc.edu -- Send compilers articles to compilers@esegue.segue.boston.ma.us {spdcc | ima | lotus| world}!esegue. Meta-mail to compilers-request@esegue.