Path: utzoo!attcan!uunet!tut.cis.ohio-state.edu!pt.cs.cmu.edu!andrew.cmu.edu!+ From: Daniel.Stodolsky@CS.CMU.EDU Newsgroups: comp.arch Subject: Beating pinout by voltage domain multiplexing Message-ID: Date: 17 Jul 90 15:05:56 GMT Organization: Carnegie Mellon, Pittsburgh, PA Lines: 27 Several recent posters have commented on the fact that many systems are currently limited by the pinout of their chips, and shrinking transistor sizes won't make this much easier. One possible solution is to go to wafer scale integration, but this brings about problems of its own. Different packaging schemes can increase the pinout somewhat, but one still gets stuck after a while. One current approach to get around this problem is (time domain) mutliplexing of the pins. The I860, for instance, mulitplexes the data bus. But this doesn't increase the maximum number of signals one can pump in or out of a chip per cycle. IDEA: Why not voltage domain multiplex? On a given pin, one signal could come in at either -3 or +3 volts for 0 and 1, and a second signal could come in at -1 or +1 volts for 0 and 1. A little extra logic would be needed to decode the signal, but one could get a doubling of the number of signals for a given packaging scheme. Of course, if your voltage sources can be precisely controlled, there's no reason why you couldn't put 3 or 4 signals per pin... Comments? Dan Stodolsky Engr. Design Research Center Carnegie Mellon University danner@miracle.edrc.cmu.edu