Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!dg-rtp!dg!Publius From: Publius@dg.dg.com (Publius) Newsgroups: comp.arch Subject: Re: Electro-optic bus Message-ID: <647@dg.dg.com> Date: 17 Jul 90 15:16:01 GMT References: Reply-To: publius@dg-pag.webo.dg.com (Publius) Distribution: comp Organization: Data General, Westboro, MA. Lines: 36 In article aglew@oberon.crhc.uiuc.edu (Andy Glew) writes: > > Throw-away idea: take, say, 4 Si microprocessors. Give them each a >point-to-point (easier to make fast) electrical interconnect (wires), >from the Si chips, to a GaAs chip. Let the GaAs chip take these 4 >sets of electrical signals, and compress them all onto a faster >optical bus that is sent back to the 4 microprocessors. > Ie. use the GaAs chip as the hub of a star, with incoming signals >in electronics, and outgoing signals in optics. > The Si chips all receive the optical signals with native Si >receivers. Sounds good to me. Just one question. How are you going to do with the clock? Is it going to be sent as one pf the signals? Or is it to be recovered by the receivers through phase-locked loops? The first approach might not work, because the high frequency of the optical bus would impose unrealistic sentivility requirement on the timing characteristics of the Si receivers. The second approach would require additional circuitry for PLL. Instead of snooping the bus, we can frequency-division-multiplex the bus. This would reduce the speed requirement on most of the receiving logic. In addition to the 4 Si microprocessors and the GaAs hub, we can have at least two "connecting" chips, which would allow us to expand the network indefinitely on a two-dimentional plat. Of course, if we have three "connecting" chips, then we can do it on three-dimention. -- Disclaimer: I speak (and write) only for myself, not my employer. Publius "Old federalists never die, they simply change their names." publius@dg-pag.webo.dg.com