Newsgroups: comp.arch Path: utzoo!henry From: henry@zoo.toronto.edu (Henry Spencer) Subject: Re: Beating pinout by voltage domain multiplexing Message-ID: <1990Jul18.161917.617@zoo.toronto.edu> Organization: U of Toronto Zoology References: Date: Wed, 18 Jul 90 16:19:17 GMT In article Daniel.Stodolsky@CS.CMU.EDU writes: >IDEA: Why not voltage domain multiplex? On a given pin, one signal >could come in at either -3 or +3 volts for 0 and 1, and a second signal >could come in at -1 or +1 volts for 0 and 1. A little extra logic would >be needed to decode the signal, but one could get a doubling of the >number of signals for a given packaging scheme... I think the big problem with this is that the chippies :-) have enough trouble getting a binary signal from chip to chip in haste. Multi-level signals will narrow the noise margins, meaning more delay to let voltages settle if you want reliable transmission. Pin count is not quite the bugaboo it used to be, with pin-grid arrays and the like avoiding the limitations of DIPs. -- NFS: all the nice semantics of MSDOS, | Henry Spencer at U of Toronto Zoology and its performance and security too. | henry@zoo.toronto.edu utzoo!henry