Path: utzoo!attcan!uunet!clyde.concordia.ca!news-server.csri.toronto.edu!cs.utexas.edu!samsung!sdd.hp.com!uakari.primate.wisc.edu!aplcen!haven!ncifcrf!lhc!usenet From: usenet@nlm.nih.gov (usenet news poster) Newsgroups: comp.arch Subject: Re: Electro-optic bus Message-ID: <1990Jul18.041829.6640@nlm.nih.gov> Date: 18 Jul 90 04:18:29 GMT References: <647@dg.dg.com> Reply-To: states@tech.NLM.NIH.GOV (David States) Distribution: comp Organization: National Library of Medicine, Bethesda, Md. Lines: 57 In article <647@dg.dg.com> publius@dg-pag.webo.dg.com (Publius) writes: >In article aglew@oberon.crhc.uiuc.edu (Andy Glew) writes: >> Throw-away idea: take, say, 4 Si microprocessors. Give them each a >>point-to-point (easier to make fast) electrical interconnect (wires), >>from the Si chips, to a GaAs chip. Let the GaAs chip take these 4 >>sets of electrical signals, and compress them all onto a faster >>optical bus that is sent back to the 4 microprocessors. >> Ie. use the GaAs chip as the hub of a star, with incoming signals >>in electronics, and outgoing signals in optics. >> The Si chips all receive the optical signals with native Si >>receivers. Wire is cheap, but it requires big expensive transistors to drive over distance or to multiple receivers. Wouldn't it make more sense to keep the GaAs transmitters local? Ie. make a module with a large silicon chip and use short, low capacitance wires to couple to a bank of GaAs optical transmiters. Then all of the off module communications would be optical and you would have better bandwidth between the silicon chip(s) and the optical "drivers". >Just one question. How are you going to do the clock? >Is it going to be sent as one of the signals? Or is it to >be recovered by the receivers through phase-locked loops? The first >approach might not work, because the high frequency of the optical bus >would impose unrealistic sensitivity requirement on the timing >characteristics of the Si receivers. The second approach would require >additional circuitry for PLL. Depends on the physical size and speed of the system you are designing. A board level machine could potentially maintain synchrony at ~50 MHz bandwidths. Larger or faster than that and you would have to recover the timing from the signal itself. >Instead of snooping the bus, we can frequency-division-multiplex the bus. >This would reduce the speed requirement on most of the receiving logic. Sounds like a more intelligent receiver that you would need for physically large systems anyway. You also gain physical simplicity (fewer lines) by multiplexing. >In addition to the 4 Si microprocessors and the GaAs hub, we can have >at least two "connecting" chips, which would allow us to expand the >network indefinitely on a two-dimentional plat. Of course, if we have >three "connecting" chips, then we can do it on three-dimention. The technology which is really going to make or break this scheme is connectors. If you can build an optical socket that couples an independently fabricated module onto board level optical channels, then you have a winner. If you can't manufacture the electrooptical modules separately or you can't make optical boards with fairly complex interconnect patterns, it is not going to fly. >-- >publius@dg-pag.webo.dg.com David States