Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!tut.cis.ohio-state.edu!rutgers!cbmvax!daveh
From: daveh@cbmvax.commodore.com (Dave Haynie)
Newsgroups: comp.arch
Subject: Re: Moto's data predicts 68040 performance well below 20 MIPS
Message-ID: <13286@cbmvax.commodore.com>
Date: 18 Jul 90 19:30:15 GMT
References: <40088@mips.mips.COM> <14900009@hpdmd48boi.hp.com> <13266@cbmvax.commodore.com> <40231@mips.mips.COM>
Reply-To: daveh@cbmvax (Dave Haynie)
Organization: Commodore, West Chester, PA
Lines: 29

In article <40231@mips.mips.COM> paulr@mips.COM (Paul Richardson) writes:

>And do not forget that the Vax 11/780 is technically not a 1 mips machine.
>The clock cycle is 200ns.

Well, if the critter did one instruction per clock cycle, like a RISC 
machine, it would only have to have a 1000ns clock cycle to be a 1 MIPS
machine.  Obviously it takes multiple clocks for the average VAX instruction
anyway, but the bigger issue is what, exactly, constitutes an instruction
in the first place.  I mean, the Transputer people have been claiming 17MIPs
for years, yet running real code a single T800 does integer stuff about
as fast as a 68020.  So for real comparisons, the further away from the
concept of MIPS you get, the better.

Strangely enough, the marketing folks at most companies still quote MIPS
and Dhrystone 1.1 figures, since they produce larger and more amazing numbers
than SPECmarks.  "These go to 11", etc.

>Peace,
>/pgr

And I'm sitting here typing this on a 25MHz 68030 based machine name "kahuna",
telnetted to a Mips-based computer sold by DEC, named "cbmvax".  All these
MIPS flying around, and a Commodore C64 could probably get this job done...

-- 
Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: hazy     BIX: hazy
	"I have been given the freedom to do as I see fit" -REM