Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!oakhill!robin
From: robin@oakhill.UUCP (Robin Edenfield)
Newsgroups: comp.arch
Subject: Re: RISC hard to program?
Message-ID: <3548@duke.oakhill.UUCP>
Date: 18 Jul 90 18:11:37 GMT
References: <40088@mips.mips.COM> <2162@opus.cs.mcgill.ca> <3648@auspex.auspex.com> <2163@opus.cs.mcgill.ca> <1145@carol.fwi.uva.nl>
Reply-To: robin@duke.UUCP (Robin Edenfield)
Organization: Motorola Inc., Austin, Texas
Lines: 19

The 68040 will only generate multilple bus cycles for misaligned
operand accesses that are non-cachable (either because the cache
is turned off or the page is non-cachable).  Writes to write through
pages that miss in the cache can also cause multiple cycles depending
on alignment because the 68040 does not write allocate for write
through pages.

Misaligned reads (or writes to copy back pages) that are cachable
will generate a line read to load the cache.  For reads, data will
be sent directly to the IU/FPU as it is received from the bus.
For a longword read at address 1, the IU will only be stalled until
the second long word of the burst is received.  The 68040 will
generate two line reads if a misaligned operand crosses a cache line
boundary.

The manual does not clearly explain how the 68040 handles these cases
(i.e. cachable, non-cachable, no allocate on write to write through).
I have sent a correction to the appropriate people.  BTW I know the
68040 data cache works this way because I designed it.