Path: utzoo!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!mcgill-vision!snorkelwacker!spdcc!esegue!compilers-sender
From: phorgan@cup.portal.com (Patrick Horgan)
Newsgroups: comp.compilers
Subject: Re: Register Allocation and Aliasing
Keywords: code, optimize
Message-ID: <1990Jul17.124057.1688@esegue.segue.boston.ma.us>
Date: 17 Jul 90 12:40:57 GMT
Sender: compilers-sender@esegue.segue.boston.ma.us
Reply-To: Patrick Horgan <phorgan@cup.portal.com>
Organization: Compilers Central
Lines: 7
Approved: compilers@esegue.segue.boston.ma.us

On Amdahl machines a data read or write to cache or register takes only
one cycle.  There is no difference.

Patrick Horgan                          phorgan@cup.portal.com
-- 
Send compilers articles to compilers@esegue.segue.boston.ma.us
{spdcc | ima | lotus| world}!esegue.  Meta-mail to compilers-request@esegue.