Path: utzoo!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!mcgill-vision!snorkelwacker!spdcc!esegue!compilers-sender
From: heggy@cs.pitt.edu (Ben Heggy)
Newsgroups: comp.compilers
Subject: Re: Register Allocation and Aliasing
Keywords: code, optimize
Message-ID: <1990Jul17.140723.2423@esegue.segue.boston.ma.us>
Date: 17 Jul 90 14:07:23 GMT
References: <1990Jul05.155937.13214@esegue.segue.boston.ma.us>
Sender: compilers-sender@esegue.segue.boston.ma.us
Reply-To: heggy@cs.pitt.edu (Ben Heggy)
Organization: Univ. of Pittsburgh Computer Science
Lines: 23
Approved: compilers@esegue.segue.boston.ma.us

In article <1990Jul05.155937.13214@esegue.segue.boston.ma.us> aglew@oberon.crhc.uiuc.edu (Andy Glew) writes:
>    Hare brained idea: allocate quantities that *might* be aliased to
>registers anyway.  Provide a register to contain the true memory
>address of the aliased quantity, which causes a trap when the address
>is accessed (or automagically forwards to/from the register). 

Any such technique must also take into account the possibility that quantities
allocated to registers may also be aliased (i.e. register addresses must also
be monitored and forwarded.)

A technique that solves this problem has been developed and a paper describing
the technique and its use has been submitted for publication. A copy of the
paper is available by sending me e-mail at heggy@cs.pitt.edu.

The paper is:
	B. Heggy and M.L. Soffa, "Architectural Support for Register 
		Allocation in the Presence of Aliasing", Submitted for
		publication.

Ben
-- 
Send compilers articles to compilers@esegue.segue.boston.ma.us
{spdcc | ima | lotus| world}!esegue.  Meta-mail to compilers-request@esegue.