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From: aglew@oberon.crhc.uiuc.edu (Andy Glew)
Newsgroups: comp.compilers
Subject: Re: Register Allocation and Aliasing
Message-ID: <1990Jul17.231509.367@esegue.segue.boston.ma.us>
Date: 17 Jul 90 23:15:09 GMT
References: <1990Jul17.124057.1688@esegue.segue.boston.ma.us>
Sender: compilers-sender@esegue.segue.boston.ma.us
Reply-To: aglew@oberon.crhc.uiuc.edu (Andy Glew)
Organization: University of Illinois, Computer Systems Group
Lines: 11
Approved: compilers@esegue.segue.boston.ma.us
In-Reply-To: phorgan@cup.portal.com's message of 17 Jul 90 12:40:57 GMT

>On Amdahl machines a data read or write to cache or register takes only
>one cycle.  There is no difference.

How many cache locations can you read/write per cycle?
And how many registers can you read/write per cycle?

--
Andy Glew, aglew@uiuc.edu
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