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From: Don_A_Corbitt@cup.portal.com
Newsgroups: comp.arch,comp.sys.intel
Subject: Re: i860 flush instruction obscurities - HELP!
Message-ID: <31793@cup.portal.com>
Date: 17 Jul 90 00:06:54 GMT
References: <15194@thorin.cs.unc.edu>
Organization: The Portal System (TM)
Lines: 25

[question about using i860 FLUSH instruction]
>     Since we are running a single process in supervisor mode, the
> caution about task switches should not apply.  What we do is use the
> address of the data buffer to be sent in the flush instruction, and
> only flush a number of cache blocks corresponding to the message
> length.  
>
>     I'd appreciate commentary from anyone in the know about what the
> flush instruction really does, why we might be having problems, and
> why the documentation claims that a cache flush area "not used to
> store data" is needed.
>    Jon Leech (leech@cs.unc.edu)    __@/

  I don't _know_ the answer to this, but my theory is that the i860 flushes
the cache by 'loading' data into the required cache block.  I expect that
FLUSH is really FLD that doesn't cause any memory reads.  This is why they
want the address of an unused block of data - it is 'loading' data from that
address, forcing out any other address.  I think you should reserve a 4KB 
block of address space that you don't use for anything else, and flush with
that.
  Just for the record, I have written a small VM kernel for the i860.  This
isn't just PRM speculation :-)
---
Don_A_Corbitt@cup.portal.com      Not a spokesperson for CrystalGraphics, Inc.
Mail flames, post apologies.       Support short .signatures, three lines max.