Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!uunet!zds-ux!gerry
From: gerry@zds-ux.UUCP (Gerry Gleason)
Newsgroups: comp.sys.m68k
Subject: Re: Moto's data predicts 68040 performance well below 20 MIPS
Message-ID: <378@zds-ux.UUCP>
Date: 16 Jul 90 15:51:52 GMT
References: <40088@mips.mips.COM>
Reply-To: gerry@zds-ux.UUCP (Gerry Gleason)
Organization: Zenith Data Systems
Lines: 25

In article <40088@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>The June 1990 issue of _IEEE_Micro_ contains an article about the
>Morotola 68040, written by some of its designers.  The article agrees
>with some of the advertising copy, saying "The sustained
>performance level is 20 VAX-equivalent MIPS and 3 Mflops at a clock
>speed of 25 MHz."  (1st paragraph, 4th sentence).

>Later in the article, Figure 2 is particularly interesting; its caption reads
>   "Processor performance relative to the 68020   versus   cache size
>    (where the 68020 equals 1)."

>For the cache sizes actually used in the 68040 (4Kbytes), the
>performance plotted in Figure 2 [68040 normalized to 68020] is in
>the range 3.6X to 4.3X, depending upon the workload.  Most of the
>benchmarks shown are at 4.1X.

Aren't you mixing apples and oranges a bit here?  The first statement
quoting 20 VAX MIPS is stated without reference to any cache, and then
you then pick from the table the data point for a 68040 without any
external cache.  You also need to know whether the 68020 they are
normalizing against has no cache, some cache, or is a theoretical
zero wait state configuration.  I'm not sure that anything can be
concluded from the information posted.

Gerry Gleason