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From: vestal@src.honeywell.com (Steve Vestal)
Newsgroups: comp.arch,comp.compilers
Subject: Re: Register Allocation and Aliasing
Keywords: code
Message-ID: <1990Jul19.182431.7087@esegue.segue.boston.ma.us>
Date: 19 Jul 90 18:24:31 GMT
References: <1990Jul06.194618.4957@esegue.segue.boston.ma.us> <1990Jul15.205606.19343@esegue.segue.boston.ma.us>
Sender: compilers-sender@esegue.segue.boston.ma.us
Reply-To: vestal@src.honeywell.com (Steve Vestal)
Organization: Compilers Central
Lines: 27
Approved: compilers@esegue.segue.boston.ma.us
In-Reply-To: mike@vlsivie.at's message of 15 Jul 90 20:56:06 GMT
Posted-Date: 19 Jul 90 17:20:47 GMT

In article <1990Jul15.205606.19343@esegue.segue.boston.ma.us> mike@vlsivie.at (Inst.f.Techn.Informatik) writes:
>   IT EVEN HAS A NAME: it's called ``cache memory''. Access times are short 
>   and if integrated on the chip can be as fast as a register access.

CRegs do have some appeal over caches for hard real-time applications.  Cache
access times can vary; many developers of hard real-time systems just disable
them.  In contrast, my impression is that CReg access times can be as
predictable as normal register access times.  This helps when determining the
worst-case execution time for a code fragment.

The problem of processor design for reliable hard real-time applications is
interesting (if often ignored).  Commercial chip developers tend to minimize
average execution time instead of minimizing worst-case execution time or
minimizing execution time variability.  Things like caches, the use of
data-dependent algorithms for artihmetic, register windowing in a way that
makes procedure call times variable, etc. causes some problems.

Does anyone have benchmark results for the current crop of microprocessors
where all caching has been disabled?

Steve Vestal
Mail: Honeywell S&RC MN65-2100, 3660 Technology Drive, Minneapolis MN 55418 
Phone: (612) 782-7049                    Internet: vestal@src.honeywell.com

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