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From: mark@hubcap.clemson.edu (Mark Smotherman)
Newsgroups: comp.arch
Subject: taxonomy for superscalars/etc
Message-ID: <9782@hubcap.clemson.edu>
Date: 21 Jul 90 16:00:20 GMT
Organization: Clemson University, Clemson, SC
Lines: 60

I would like to suggest a possible taxonomy to distinguish among
the differing organizations of new processors.  Your comments
and corrections are welcome.

I see three major areas: issue parallelism, start of execution
(which can differ from time of issue if it is the responsibility
of the functional unit to obtain its own operands), and resource
naming (specifically registers).

Thus I would like to give a three-part classification, i/e/n,
to each machine.  The first field would be issue parallelism:

  (1) single issue per cycle
  (s) superscalar issue of independent instructions
  (v) vliw issue in which several opcodes or instructions (i.e. i860)
      are grouped into a wide instruction word

The second field would be execution start time:

  (d) data dependencies (RAW) are interlocked by issue unit, which
      stalls until resolution; the fn unit starts upon issue since
      issue unit provides both the op specification as well as the
      operands
  (c) compiler must reorder instructions to avoid data dependencies
  (x) out-of-order execution, where the fn unit starts only after
      obtaining its operands -- the issue unit does not stall on
      data dependencies but forces the fn unit to resolve them

The third field would be resource naming, specifically register
renaming:

  (p) physical registers named in instructions -- must be concerned
      about anti-dependencies (WAR) and output dependencies (WAW)
  (r) hardware renames logical registers in instructions by tagging
      or assignment of physical registers (removes WAR and WAW)

Using this proposed taxonomy, I would classify the following machines:

  MIPS R3000                  1 / c / p
  MIPS R6000                  1 / d / p
  Motorola 88K                1 / d / p

  Intel i860                  v / d / p
  Multiflow Trace             v / c / p

  Apollo DN10000              s / d / p  ??
  Intel i960                  s / d / p
  Tandem Cyclone              s / d / p  ??

  CDC 6600                    1 / x / p

  IBM S/360 M91 (Tomasulo)    1 / x / r
  Nexgen F86                  1 / x / r

  Metaflow Lightning (SPARC)  s / x / r  ??
  IBM RS/6000                 s / x / r

-- 
Mark Smotherman, Comp. Sci. Dept., Clemson University, Clemson, SC 29634
INTERNET: mark@hubcap.clemson.edu    UUCP: gatech!hubcap!mark