Path: utzoo!utgpu!watserv1!watmath!att!rutgers!bellcore-2!bellcore!messy!mo
From: mo@messy.bellcore.com (Michael O'Dell)
Newsgroups: comp.arch
Subject: Re: Is handling off-alignment important? (was Re: RISC hard to program?)
Message-ID: <25583@bellcore.bellcore.com>
Date: 22 Jul 90 05:50:41 GMT
References: <104037@convex.convex.com> <8840014@hpfcso.HP.COM> <1990Jul22.001925.8979@zoo.toronto.edu>
Sender: news@bellcore.bellcore.com
Reply-To: mo@messy.UUCP (Michael O'Dell)
Organization: Center for Chaotic Repeatabilty
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Once again Henry demonstrates that his powers of subtle understatement
are exceeded only by his occassional correctness.

Regretably, simply choosing to build a RISC doesn't obviate all those
awful problems. In machines of any flavor (RISC or CISC) where the backend
which detects the pagefaults can't talk to the front-end which needs
to stop fetching the wrong instructions because, say, the speed of light
on real circuit boards is so pokey, traps are nightmares of astounding
proportions.  Interrupts aren't as bad because they are not required
to be particularly synchronized with the instruction stream.
But those atomic, synchronous traps are genuine gut busters in both
hardware and software.

	-Mike