Path: utzoo!attcan!uunet!mcsun!ukc!edcastle!dcl-cs!aber-cs!thor!pcg
From: pcg@cs.aber.ac.uk (Piercarlo Grandi)
Newsgroups: comp.arch
Subject: Re: Is handling off-alignment important? (was Re: RISC hard to program?)
Message-ID: <PCG.90Jul23162542@thor.cs.aber.ac.uk>
Date: 23 Jul 90 15:25:42 GMT
References: <104037@convex.convex.com> <8840014@hpfcso.HP.COM>
	<1990Jul22.001925.8979@zoo.toronto.edu>
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In-reply-to: henry@zoo.toronto.edu's message of 22 Jul 90 00:19:25 GMT


In article <1990Jul22.001925.8979@zoo.toronto.edu> henry@zoo.toronto.edu
(Henry Spencer) writes:

   If you want *real* fun, consider that unaligned operands can overlap.
   Think about the implications of overlapping operands that span a page
   boundary between a normal page and a paged-out read-only page in a
   machine with two levels of virtual-address cache and a deep pipeline...
   with an exception-handling architecture that was nailed down in detail
   on much slower and simpler implementations, and can't be changed.  This
   is the sort of problem that makes chip designers quietly start sending
   their resumes to RISC manufacturers... :-)

For the interested, the MU5 supercomputer from Manchester was virtually
like this (except that they were designing it from scratch). They solved
the problem by strict design discipline, as you can find in "The MU5
computer system", Ibbett & Morris (MacMillan).  Basically they found out
that the only sensible way out is to have restartable, not continuable,
instructions. Saving processor state on a fault is a very bad idea if it
is complicated. You substitute for this the easier problem of
idempotency.
--
Piercarlo "Peter" Grandi           | ARPA: pcg%cs.aber.ac.uk@nsfnet-relay.ac.uk
Dept of CS, UCW Aberystwyth        | UUCP: ...!mcsun!ukc!aber-cs!pcg
Penglais, Aberystwyth SY23 3BZ, UK | INET: pcg@cs.aber.ac.uk