Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!know!zaphod.mps.ohio-state.edu!usc!apple!oliveb!orc!bbn.com!oak.bbn.com
From: schooler@oak.bbn.com (Richard Schooler)
Newsgroups: comp.arch
Subject: High-Priority Instructions
Message-ID: <58428@bbn.BBN.COM>
Date: 25 Jul 90 15:26:02 GMT
Sender: news@bbn.com
Reply-To: schooler@oak.bbn.com (Richard Schooler)
Organization: BBN Advanced Computers, Inc.
Lines: 21


  The Motorola 88100's register file has only a single write port, and
thus on each cycle, only a single instruction can write a result.  This
is known as the "writeback slot".  When carefully hand-scheduling code
(and thinking about scheduling algorithms), the writeback slot can be a
real pain, mainly because of the fixed priority scheme: if instructions
of different latency contend for the writeback slot, then the integer
unit gets it first, then floating-point instructions, then loads
(roughly).  However, it often happens that loads or floating-point
instructions are on the critical path, and can get stalled because of
other instructions stealing the writeback slot.  Dealing with this is
painful by hand, and I haven't been able to come up with reasonable
algorithms, either.
  I thus propose that instructions have a "high-priority" bit, which the
compiler would place on critical-path instructions that would otherwise
get delayed.  Ties between instructions of the same priority would be
broken by the usual rules.  The scheduler could then mostly ignore the
writeback slot.  What do you think?

	-- Richard
	schooler@bbn.com