Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!umich!umeecs!billms
From: billms@caen.engin.umich.edu (Bill Mangione-Smith)
Newsgroups: comp.arch
Subject: Re: RS/6000 renaming
Message-ID: <2965@zipeecs.umich.edu>
Date: 26 Jul 90 22:21:53 GMT
References: <1990Jul26.160540.15289@mozart.amd.com> <9871@hubcap.clemson.edu>
Sender: news@zip.eecs.umich.edu
Organization: University of Michigan Engineering, Ann Arbor
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In article <9871@hubcap.clemson.edu> mark@hubcap.clemson.edu (Mark Smotherman) writes:
 >From davec@nucleus.amd.com (Dave Christie):
 >> 
 >> Are you implying that two FP instructions can be issued in one cycle?!
 >> I don't believe this is the case.
 >
 >Yes, the instruction dispatch on RS/6000 does not require a matched
 >pair of an integer instruction and a flt.pt. instruction in order to
 >dispatch (issue?) 

Nope, this is not quite true.  One FP instruction can be issued by the 
FPU each clock, though it can be a mult-add.  Two can be sent (i.e. dispatched)
to the FPU each clock, but atleast one of them sits there in a queue.  This
removes one more worry from the compiler about matching up instructions
for dispatching from the I cache unit.

>Mark Smotherman, Comp. Sci. Dept., Clemson University, Clemson, SC 29634

Bill Mangione-Smith
billms@eecs.umich.edu