Path: utzoo!attcan!uunet!aplcen!samsung!cs.utexas.edu!wuarchive!emory!hubcap!mark
From: mark@hubcap.clemson.edu (Mark Smotherman)
Newsgroups: comp.arch
Subject: Re: RS/6000 renaming
Message-ID: <9871@hubcap.clemson.edu>
Date: 26 Jul 90 20:14:10 GMT
References: <1990Jul26.160540.15289@mozart.amd.com>
Organization: Clemson University, Clemson, SC
Lines: 31

From davec@nucleus.amd.com (Dave Christie):
> 
> Are you implying that two FP instructions can be issued in one cycle?!
> I don't believe this is the case.

Yes, the instruction dispatch on RS/6000 does not require a matched
pair of an integer instruction and a flt.pt. instruction in order to
dispatch (issue?) multiple instructions per cycle (as does the i860
in DIM and the i960CA).

From H. Bakoglu and T. Whiteside, "RISC System/6000 Hardware Overview,"
in IBM RISC System/6000 Technology, 1990, order no. SA23-2619, p. 11:

	Four instructions per cycle can be fetched from the I-cache
	arrays to the instruction buffers and dispatch unit, which
	can dispatch up to four instructions per cycle.  Two of these
	are internal dispatches to the ICU (branches and condition
	register instructions) and two are external dispatches to
-->	the FXU and FPU.  There is no restriction on the combination
-->	of instructions that are dispatched to the FXU and FPU.  They
-->	can be a fixed- and a floating-point instruction, or two
-->	fixed-point instructions, or two floating-point instructions.
	Because the fixed- and floating-point instructions are not mated
	together, instruction dispatch bandwidth or code space is not
	wasted.  [The FXU and FPU both have instruction buffers with
	12 entries each to even out the dispatching patterns.]

Very nice.
-- 
Mark Smotherman, Comp. Sci. Dept., Clemson University, Clemson, SC 29634
INTERNET: mark@hubcap.clemson.edu    UUCP: gatech!hubcap!mark