Path: utzoo!attcan!uunet!samsung!usc!snorkelwacker!spdcc!esegue!compilers-sender
From: lupine!rfg@uunet.UU.NET (Ron Guilmette)
Newsgroups: comp.compilers
Subject: Re: Register Allocation and Aliasing
Keywords: code, optimize
Message-ID: <1990Jul19.182138.6854@esegue.segue.boston.ma.us>
Date: 19 Jul 90 18:21:38 GMT
References: <1990Jul17.124057.1688@esegue.segue.boston.ma.us>
Sender: compilers-sender@esegue.segue.boston.ma.us
Reply-To: lupine!rfg@uunet.UU.NET (Ron Guilmette)
Organization: Network Computing Devices, Inc., Mt. View, CA
Lines: 14
Approved: compilers@esegue.segue.boston.ma.us

In article <1990Jul17.124057.1688@esegue.segue.boston.ma.us> Patrick Horgan <phorgan@cup.portal.com> writes:
>On Amdahl machines a data read or write to cache or register takes only
>one cycle.  There is no difference.

Gee!  I guess that Amdahl's *never* get cache misses!

Now why didn't anybody mention that to me when I worked there? ;-)

-- 

// Ron Guilmette (rfg@ncd.com)
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