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From: savel@hoss.unl.edu (Bharat P. Savel)
Newsgroups: comp.lsi.cad
Subject: VHDL- need help
Message-ID: <1990Jul26.011329.15635@hoss.unl.edu>
Date: 26 Jul 90 01:13:29 GMT
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Organization: Computing Resource Center, University of Nebraska
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i am having a problem on the VHDL compiler; i have an entity, of which i
am using only 3 out of the 10 ports declared; i had hoped to declare them
as 'open' at the time of instantization; however i am getting an error
saying that i need to give a default value to the port of IN modes ( ??
where in) and i exhausted all combinations; suggestions anyone?
-savel