Path: utzoo!attcan!uunet!aplcen!samsung!usc!ucsd!ucbvax!husc6!encore!pinocchio.encore.com
From: jkenton@pinocchio.encore.com (Jeff Kenton)
Newsgroups: comp.sys.m88k
Subject: Re: Some basic questions regarding use of 88000
Message-ID: <12290@encore.Encore.COM>
Date: 24 Jul 90 15:50:50 GMT
References: <1990Jul24.032416.13340@cec1.wustl.edu>
Sender: news@Encore.COM
Lines: 18

From article <1990Jul24.032416.13340@cec1.wustl.edu>, by kapoor@wuee1.wustl.edu (Sanjay Kapoor):
> 
> Q1: How does the 88000 handle interrupts? the sparc architecture helps
> reduce the overhead for critical interrupts by reserving a register window for
> trap handling. What about M88000?
> 

The simple answer is that the processor traps to Exception Vector 1 (0 is reset)
and the exception handling code does the rest.  "The rest" includes saving
registers, processing anything in the data or FP pipelines, figuring out which
device interrupted (and processing the interrupt), and restoring the interrupted
state.


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      jeff kenton  ---	temporarily at jkenton@pinocchio.encore.com	 
		   ---  always at (617) 894-4508  ---
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