Path: utzoo!attcan!uunet!tut.cis.ohio-state.edu!zaphod.mps.ohio-state.edu!usc!jarthur!nntp-server.caltech.edu!laguna.ccsf.caltech.edu!daveg From: daveg@near.cs.caltech.edu (Dave Gillespie) Newsgroups: comp.arch Subject: Re: High-Priority Instructions Message-ID: Date: 28 Jul 90 22:24:06 GMT References: <58428@bbn.BBN.COM> <37310@shemp.CS.UCLA.EDU> <1990Jul27.161856.25701@mozart.amd.com> Sender: news@laguna.ccsf.caltech.edu Organization: California Institute of Technology Lines: 14 In-Reply-To: davec@nucleus.amd.com's message of 27 Jul 90 16:18:56 GMT I don't have the book handy, but as I recall the highest priority on the 88000's writeback slot was given to the single-cycle instructions. I always figured this was so that these instructions could be guaranteed to complete in one cycle. So, yes, other strategies like first-come-first-served might work better, but they would have complicated the part of the processor that was trying to be simplest and fastest. Just my guess, -- Dave -- Dave Gillespie 256-80 Caltech Pasadena CA USA 91125 daveg@csvax.caltech.edu, ...!cit-vax!daveg