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From: owen@sbcs.sunysb.edu (Owen Kaser)
Newsgroups: comp.arch
Subject: Do chip timing specs mean anything?
Message-ID: <1990Aug4.152038.1132@sbcs.sunysb.edu>
Date: 4 Aug 90 15:20:38 GMT
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Organization: State University of New York at Stony Brook
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Do timing specs for microprocessors and their support chips bear
any relation to reality, and do industrial designers 
(need to) pay any heed to them?  Here's the background for my question:

I did a number of microprocessor-based designs during my stay
at a small company a couple of years ago.  For the first, I was told which 
major parts were to be used (uP, serial controllers, etc), and what
the desired clock speed was (it was high).  So I set to work, doing
the design the way I thought such were supposed to be done.  A couple
of weeks later I presented a preliminary design to my boss.  He glanced
at it and told me it had too many chips.  I explained that the ones to
which he was objecting were part of a wait-state generator, and that
it was required because timing analysis (from specs) showed that fast
enough peripheral chips/ memories were either not available or were too
expensive.  He chuckled at me for being naive, and told me not to worry
about meeting timing specs: such chips always ran much better than 
their worst case specs, even though our bus loads may have exceeded 
the test load.  I was quite dubious about the wisdom of this approach, 
but he was the boss...  

I made a long list of all the timing violations (under worst case conditions) 
that the specs suggested, expecting to have a lot of debugging to do
before the product was in (successful) volume production.  After the
first prototype units came in (and the other problems ironed out),
I attacked them with a 'scope, to see how bad things were.
At room temperature, timing was great, even using alternate manufacturers 
parts.  Even when heated well above our spec'd operating temp 
(and cooled too), the units continued to run.

Now the pressure seemed a little worse, since I had to release them to
manufacturing, and I did not like the risk of flakiness. Nevertheless
I did so, and despite the usual little problems (not timing related), 
several hundred were produced (until I left the company), with no evidence of
any timing problems.

(My boss had done the previous designs, which had horrendous (worst case)
timing violations.  10k's of these were produced over several years.  No
problems were observed. Due to a 3 year warranty we saw field failures,
but I don't recall any traced to timing)

What is the moral of this story?  Usually perhaps 30% better performance
than indicated was required, and the chips delivered it.  Was it because
the chips had been around long enough that the manufacturers had improved
them and not updated their data books?  Was it that the specs were good
until 70 degrees C, and we never rose above 55 degrees C?  Were we
just lucky, and will the units stop working after the chips age
(electromigration etc)?

If I reverse engineer other uP-based designs, will I see widespread 
spec violations?  If I reverse engineer a mainframe?  If I reverse engineer
*your* designs? 

Note: don't ignore power-handling specs!  My boss tried that too, 
and I saw the results in his power supplies...  
But that's not a comp.arch topic.