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From: lundeby@hpldola.HP.COM (Bruce Lundeby)
Newsgroups: comp.lsi.cad
Subject: Re: VHDL- need help
Message-ID: <1460002@hpldola.HP.COM>
Date: 27 Jul 90 21:15:25 GMT
References: <1990Jul26.011329.15635@hoss.unl.edu>
Organization: HP Elec. Design Div. -ColoSpgs
Lines: 37

i am having a problem on the VHDL compiler; i have an entity, of which i
am using only 3 out of the 10 ports declared; i had hoped to declare them
as 'open' at the time of instantization; however i am getting an error
saying that i need to give a default value to the port of IN modes ( ??
where in) and i exhausted all combinations; suggestions anyone?
-savel
 
----------

Try placing default values on the in mode ports of your local component
declarations.

For example:

architecture EXAMPLE of CKT is
    ...	
    signal SIG1: MVL;
    signal SIG2: MVL;
    ...	
    component AND3
	port (A: in MVL := 'X';   -- note defaults here
	      B: in MVL := 'X';
	      C: in MVL := 'X';
	      Y: out MVL);
    end component;
begin
    ...
    CMP_N: AND3
	port_map (A => SIG1,
		  B => open,
		  C => open,
		  Y => SIG2);
    ...
end EXAMPLE;

Bruce Lundeby
lundeby@hpldola.hp.com