Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!cs.utexas.edu!sdd.hp.com!elroy.jpl.nasa.gov!ames!dftsrv!mimsy!chris From: chris@mimsy.umd.edu (Chris Torek) Newsgroups: comp.arch Subject: Re: Is handling off-alignment important? Message-ID: <25900@mimsy.umd.edu> Date: 5 Aug 90 21:42:20 GMT References: <104037@convex.convex.com> <8840014@hpfcso.HP.COM> <2357@crdos1.crd.ge.COM> Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742 Lines: 37 In article <2357@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) writes: (in response to `what if the word being loaded spans a page boundary and the second page is invalid) >... restart the instruction. Using an LRU scheme the 1st page >would not get paged out unless the physical mapping was 1 page/process. >... pages for code, stack, source of copy instruction, dest of >copy instruction. If you allow unalligned access you need two pages in >each area to handle access over a boundary, that totals eight. No, I >wouldn't want to actually run a system with that little memory. Actually, it is (or can be) even worse than that. Consider the following VAX gem: addl3 *0(r1),*0(r2),*0(r3) Assume that the instruction itself (which is 7 bytes long) crosses a page boundary, that r1, r2, and r3 contain 0x1ff, 0x3ff, and 0x5ff respectively, that the longword at 0x1ff..0x203 contains 0x7ff, that the longword at 0x3ff..0x403 contains 0x9ff, and that the longword at 0x5ff..0x603 contains 0xbff. Then we need: 2 pages for the instruction 2 pages for 0(r1) (0x1ff..0x203) 2 pages for 0(r2) (0x3ff..0x403) 2 pages for 0(r3) (0x5ff..0x603) 2 pages for *1ff (0x7ff..0x803) 2 pages for *3ff (0x9ff..0xa03) 2 pages for *5ff (0xbff..0xc03) -- total 14 pages for one `simple' `addl3' instruction. (Imagine the fun with a six-argument instruction like `index'!) -- In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7163) Domain: chris@cs.umd.edu Path: uunet!mimsy!chris (New campus phone system, active sometime soon: +1 301 405 2750)