Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!tut.cis.ohio-state.edu!pt.cs.cmu.edu!MATHOM.GANDALF.CS.CMU.EDU!lindsay
From: lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: Do chip timing specs mean anything?
Message-ID: <10141@pt.cs.cmu.edu>
Date: 7 Aug 90 18:42:12 GMT
References: <1990Aug4.152038.1132@sbcs.sunysb.edu> <712@dg.dg.com> <1990Aug7.140840.14044@mlb.semi.harris.com>
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Organization: Carnegie-Mellon University, CS/RI
Lines: 27

In article <1990Aug7.140840.14044@mlb.semi.harris.com> 
	krl@jujeh.mlb.semi.harris.com (Ken Lyons) writes:
>The problem with using parts out of spec is that the distribution changes
>over time.  Most of the time this is for the better as manufacturing
>technology improves.

I recall a customer who designed to the values he measured on
_prototype_ parts.  If memory serves, it was a European telecomm
company, buying single-chip op amps from BNR.  They ordered several
hundred thousand chips - and BNR ran them off on the main production
line, rather than on the high-profile prototype line.  Did they meet
the specs?  Yes.  Did _any_ of the customer's boards work?  No - not
until a kludge socket was designed.  

[For the uninitiated: a kludge socket is a socket-on-a-socket.  It
provides a place for a few extra components, or even for a tiny
mezzanine board.  Now, why would they do that? - 'cause they'd
already manufactured the circuit boards, that's why. Ouch.]

The dream of the "self timed" designs is that they will automatically
be immune to timing problems.  Worst-cases, heat, aging, changes by
vendors, changes of vendor - all of these are just non-problems,
except in that the overall product's speed may occasionally surprise
you.  Anyone out there working on these things, please let us know
how it's going.
-- 
Don		D.C.Lindsay