Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!cbmvax!daveh
From: daveh@cbmvax.commodore.com (Dave Haynie)
Newsgroups: comp.arch
Subject: Re: Do chip timing specs mean anything?
Message-ID: <13706@cbmvax.commodore.com>
Date: 8 Aug 90 16:37:42 GMT
References: <1990Aug4.152038.1132@sbcs.sunysb.edu> <712@dg.dg.com> <1990Aug7.140840.14044@mlb.semi.harris.com> <66356@sgi.sgi.com>
Reply-To: daveh@cbmvax (Dave Haynie)
Distribution: na
Organization: Commodore, West Chester, PA
Lines: 24

In article <66356@sgi.sgi.com> rpw3@sgi.com (Rob Warnock) writes:

>For example, one tends to assume without ever questioning it that the 
>minimum clock-to-Q of a flip-flip is greater than the input hold time of 
>that same part number. If this *weren't* true, you couldn't build reliable 
>shift registers with those parts. 

Actually, this came up recently in a real situation in my work.  At least in
simulations, some gate array flip-flops were asserting that they're clock to
output delay was shorter than their input hold time.  There was a bit of
debate about this situation.  I was claiming that such a device, while 
possibly useful in some situations, does not behave as a true D-type flip
flop.  At least any kind of D-type flip-flop that a system-level circuit
designer has enountered -- these chip designers with their dynamic latches 
and other weird critters may be used to stranger things that this.

>Rob Warnock, MS-9U/510		rpw3@sgi.com		rpw3@pei.com
>Silicon Graphics, Inc.		(415)335-1673		Protocol Engines, Inc.


-- 
Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
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      Get that coffee outta my face, put a Margarita in its place!