Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!cs.utexas.edu!wuarchive!brutus.cs.uiuc.edu!ux1.cso.uiuc.edu!ux1.cso.uiuc.edu!aglew From: aglew@dual.crhc.uiuc.edu (Andy Glew) Newsgroups: comp.arch Subject: Re: Is handling off-alignment important? Message-ID: Date: 10 Aug 90 02:14:10 GMT References: <104037@convex.convex.com> <8840014@hpfcso.HP.COM> <2357@crdos1.crd.ge.COM> <25900@mimsy.umd.edu> <2392@crdos1.crd.ge.COM> <1990Aug8.212255.3555@zoo.toronto.edu> <46171@ism780c.isc.com> Sender: usenet@ux1.cso.uiuc.edu (News) Organization: University of Illinois, Computer Systems Group Lines: 22 In-Reply-To: news@ism780c.isc.com's message of 9 Aug 90 18:44:40 GMT >There was at least one design group (an SEL machine) that noticed that they >could encode the operand width using the low order address bits. In this >way they were able to save a bit in the instruction thus providing an >additional address bit. Of course, there was no such concept as misaligned >access reference using this scheme. > > Marv Rubinstein SEL became Gould CSD, and then... The last Gould machines used the low order bits of the offset field (which was present on all memory access instructions) as part of the width encoding. They did not, however, use the low order bits of the registers, and they did produce misaligned traps if the low order bits of the final address, ignoring the low order bits of the offset literal, were incorrect. This meant that you could not have an odd register, and add 1 to it via the addressing mode to make a correctly aligned even address. It never caused me any problems - it even found a few bugs. -- Andy Glew, a-glew@uiuc.edu [get ph nameserver from uxc.cso.uiuc.edu:net/qi]