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From: mea@cbnewse.att.com (mark.e.anderson)
Newsgroups: comp.arch
Subject: Re: Do chip timing specs mean anything?
Message-ID: <1990Aug10.013400.5171@cbnewse.att.com>
Date: 10 Aug 90 01:34:00 GMT
References: <1990Aug4.152038.1132@sbcs.sunysb.edu>
Distribution: na
Organization: AT&T Bell Laboratories
Lines: 45

In article  owen@sbcs.sunysb.edu (Owen Kaser) writes:
>Do timing specs for microprocessors and their support chips bear
>any relation to reality, and do industrial designers 
>(need to) pay any heed to them?  

When I was a chip designer, we used to negotiate timing parameters
with the system designers which would initially be alot of guesswork
based upon what VLSI technology we were planning to use.  The system
designers would push for reduced wait states and we would push
for more leeway in our design.  Eventually, an agreement would be
made and the specification drawn up.

After a design was made, it sometimes became apparent that we would far
exceed the max timing parameters but we wouldn't change the
spec unless  absolutely necessary.   Commercial chip specs are
probably driven more by marketiers but I can imagine that
the chip designers behind the scenes are trying to negotiate
the longest times possible.

Sometimes timing analysis can involve alot of handwaving.  Usually,
chip timing is speced upon a set output capacitance, like 50pfs.  Sometimes,
it is hard to estimate exactly what the capacitance is going
to be.   Once we had a really tight timing on some RAMs that
were hooked to our chip's bi-directional bus.  We were down to
the nano-second, worst case scenerio, and in order to get that
extra cushion, I was able to get  35pf load put into the spec
instead of 50.  The bus only went one place so it was a proper
judgement to make.

There are companies that don't seem to understand worst case timing.
One large gate array maker provided us with worst case simulations
for this one gate array we needed.  When we got the initial prototypes,
all the protoype timing matched the worst case simulations.  And this
was their nominal lot.   Fortunately, for us, we had access to a 
Takeda to run shmoos and catch this.  There are probably alot of smaller 
companies who design these things, plug them in a board not knowing 
how close they are to a worst-case design.

Anyway, ask any gray haired engineer and you probably
won't find one that would suggest violating worst case timing
parameters.


Mark
mea@ihlpl.att.com