Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!iuvax!maytag!watstat!dmurdoch
From: dmurdoch@watstat.uwaterloo.ca (Duncan Murdoch)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: NMI Breakout (was: Parity error handling under DOS?)
Message-ID: <1990Aug11.033457.12369@maytag.waterloo.edu>
Date: 11 Aug 90 03:34:57 GMT
References: <9008101543.aa18551@PARIS.ICS.UCI.EDU> <1260@gold.GVG.TEK.COM>
Sender: daemon@maytag.waterloo.edu (Admin)
Organization: University of Waterloo
Lines: 26

In article <1260@gold.GVG.TEK.COM> grege@gold.GVG.TEK.COM (Greg Ebert) writes:
>>
>In the AT, and probably the PC, there is an NMI mask register which allows you
>to disable IO_CHANNEL_CHECK interrupts. 

Yes, it's there in the XT, at least.  And by default, in some BIOS's at least,
it's left disabled.  Lots of languages (MS Fortran I think, old Turbo Pascal,
etc.) forget to enable it, and crash when they cause an exception on
the math coprocessor (which shares the interrupt, for some reason).

>I believe the mask register is in port 70h, bit 7. It's been awhile since I
>did that ASIC for AST Research, which had the NMI register inside. I
>think writing a '1' to this position disables NMI's.

On an XT, writing 80h to port A0h enables it.

Now, for my question:  The current issue of PC Techniques (a new programming
mag, generally pretty good) gives instructions (p. 8) to build a simple
breakout switch, that triggers a NMI by temporarily grounding bus pin A1.
I did it, but get no sign of anything happening, whether NMI is enabled or
not.  (This on a no-name 8086 clone.)  

Can anyone suggest a fix?  What do I need to do to get an NMI?

Duncan Murdoch
dmurdoch@watstat.waterloo.edu