Path: utzoo!attcan!uunet!samsung!zaphod.mps.ohio-state.edu!sdd.hp.com!hp-pcd!hpvcfs1!johne
From: johne@hpvcfs1.HP.COM (John Eaton)
Newsgroups: comp.arch
Subject: Re: Do chip timing specs mean anything?
Message-ID: <1080006@hpvcfs1.HP.COM>
Date: 15 Aug 90 17:24:48 GMT
References: <1990Aug4.152038.1132@sbcs.sunysb.edu>
Organization: Hewlett Packard, Vancouver, WA
Lines: 22

<<<<
< expensive.  He chuckled at me for being naive, and told me not to worry
< about meeting timing specs: such chips always ran much better than 
< their worst case specs, even though our bus loads may have exceeded 
< the test load.  I was quite dubious about the wisdom of this approach, 
< but he was the boss...  
----------
Simply say, "Put that in writing and SIGN it"


BTW, Does anyone worry about Best Case/Worst Case analysis? Its easy to
anaylze a circuit if you assume that everything is at worst case but that
will probably never occur. What you will see is some combination of timings
that fall between best and worst. (Best in many cases is not even speced).
How do you analyze the semi-infinite number of possible timings that a typical
circuit can experiance?


John Eaton
!hpvcfs1!johne