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From: baxter@zola.ics.uci.edu (Ira Baxter)
Newsgroups: comp.arch
Subject: Re: Do chip timing specs mean anything?
Message-ID: <26C9CE2F.3723@ics.uci.edu>
Date: 15 Aug 90 22:35:27 GMT
References: <1990Aug4.152038.1132@sbcs.sunysb.edu> <1080006@hpvcfs1.HP.COM>
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In <1080006@hpvcfs1.HP.COM> johne@hpvcfs1.HP.COM (John Eaton) writes:

>BTW, Does anyone worry about Best Case/Worst Case analysis? Its easy to
>anaylze a circuit if you assume that everything is at worst case but that
>will probably never occur. What you will see is some combination of timings
>that fall between best and worst. (Best in many cases is not even speced).

I used to see lots of designs in which delays were manufactured by chaining
a number of inverters (4 or more) from the same package in a row.
The only designer I ever talked to about this stunt mumbled something
about the law of large (4 is large?) numbers and statistics making the
delay through these circuits pretty stable.

I didn't believe him.  But I think power supplies are often designed
under the assumption of average current drain on parts, not worst case.

--
Ira Baxter