Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!cs.utexas.edu!usc!apple!amdcad!mozart.amd.com!neutron!davec From: davec@neutron.amd.com (Dave Christie) Newsgroups: comp.arch Subject: Re: Do chip timing specs mean anything? Message-ID: <1990Aug16.022601.6583@mozart.amd.com> Date: 16 Aug 90 02:26:01 GMT References: <1990Aug4.152038.1132@sbcs.sunysb.edu> <1080006@hpvcfs1.HP.COM> Sender: usenet@mozart.amd.com (Usenet News) Reply-To: davec@nucleus.amd.com (Dave Christie) Organization: Advanced Micro Devices, Inc., Austin, Texas Lines: 31 In article <1080006@hpvcfs1.HP.COM> johne@hpvcfs1.HP.COM (John Eaton) writes: > >BTW, Does anyone worry about Best Case/Worst Case analysis? Its easy to >anaylze a circuit if you assume that everything is at worst case but that >will probably never occur. What you will see is some combination of timings >that fall between best and worst. (Best in many cases is not even speced). >How do you analyze the semi-infinite number of possible timings that a typical >circuit can experiance? Absolutely. For large synchronous systems, such as mainframes, done with SSI/MSI (I know - prehistoric times, but this applies equally well to gate array implementations) where one has to deal with skew in the clock distribution network, one has to worry about short paths as well as long paths (although they tend to be much less common). In a previous life at a mainframe company we designed taking both limits into account, and vendors had to supply best and worst case specs. As long as you use only synchronous logic (i.e. no f/fs with asynchronous set/reset) then you don't care about in-between timings. You just make sure that everything at worst case meets set-up times, and best case meets hold times (to simplify somewhat). So you only need to analyze two cases. (We had in-house static timing analysis software that made this relatively easy, analyzing paths through combinatorial logic that were bounded by edge-triggered devices. Had to live with some artificially imposed restrictions on our designs for the sake of the software, though.) I have heard that IBM actually designs to statistically-derived timing rules, a sort of likeliest-worst-case methodology as opposed to absolute worst case - lets them push the clock a bit more. But then, with their volume and prices, they can afford a less-than-100% yield... ------------------- Dave Christie My opinions only.