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From: roy@phri.nyu.edu (Roy Smith)
Newsgroups: comp.arch
Subject: Re: Do chip timing specs mean anything?
Message-ID: <1990Aug16.144744.21058@phri.nyu.edu>
Date: 16 Aug 90 14:47:44 GMT
References: <1990Aug4.152038.1132@sbcs.sunysb.edu> <1080006@hpvcfs1.HP.COM> <26C9CE2F.3723@ics.uci.edu>
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baxter@zola.ics.uci.edu (Ira Baxter) writes:
> delays were manufactured by chaining a number of inverters (4 or more)
> from the same package in a row.  The only designer I ever talked to about
> this stunt mumbled something about the law of large (4 is large?) numbers
> and statistics making the delay through these circuits pretty stable.

	I assume the idea here is that, while you can't count on the delay
through a single gate being constant, if you sum 4 delays, some will be
fast and some slow, so they average out.

	Eeek!  I won't argue on one side or the other of the "is 4 a large
sample" question, but to assume that 4 gates on the same chip have
statistically independant delays seems to me to be exactly the opposite of
what you should assume.  I would say that using 4 gates from the same chip
is what you should do if you want to make sure the delays match each other
as closely as possible, and track each other under varying environmental
conditions.

	Not only will all 4 gates be subject to the same inter-batch and
inter-manufacturer variations, but they will have aged the same amount,
have been subjected to the same history of abuse and/or proper care, and
will see the same power supply and temperature conditions, not to mention
EMF, radiation, POM, etc.
--
Roy Smith, Public Health Research Institute
455 First Avenue, New York, NY 10016
roy@alanine.phri.nyu.edu -OR- {att,cmcl2,rutgers,hombre}!phri!roy
"Arcane?  Did you say arcane?  It wouldn't be Unix if it wasn't arcane!"