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From: keith@mips.COM (Keith Garrett)
Newsgroups: comp.arch
Subject: Re: Do chip timing specs mean anything?
Message-ID: <40889@mips.mips.COM>
Date: 16 Aug 90 16:58:51 GMT
References: <1990Aug4.152038.1132@sbcs.sunysb.edu> <1080006@hpvcfs1.HP.COM>
Sender: news@mips.COM
Reply-To: keith@mips.COM (Keith Garrett)
Organization: MIPS Computer Systems, Inc.
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In article <1080006@hpvcfs1.HP.COM> johne@hpvcfs1.HP.COM (John Eaton) writes:
>BTW, Does anyone worry about Best Case/Worst Case analysis? Its easy to
>anaylze a circuit if you assume that everything is at worst case but that
>will probably never occur. What you will see is some combination of timings
>that fall between best and worst. (Best in many cases is not even speced).
>How do you analyze the semi-infinite number of possible timings that a typical
>circuit can experiance?
>
you can't. you just look at the corners and the middle, and hope that the test
guys have taken care of other anomalies. fortunately, things tend to track
(ie. longer output delays and shorter setup times tend to go together).

	keith
-- 
Keith Garrett        "This is *MY* opinion, OBVIOUSLY"
      Mips Computer Systems, 930 Arques Ave, Sunnyvale, Ca. 94086
      (408) 524-8110     keith@mips.com  or  {ames,decwrl,prls}!mips!keith