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From: jackk@shasta.Stanford.EDU (jackk)
Newsgroups: comp.arch
Subject: Re: Do chip timing specs mean anything?
Message-ID: <27@shasta.stanford.edu>
Date: 16 Aug 90 18:30:38 GMT
References: <1990Aug4.152038.1132@sbcs.sunysb.edu> <1080006@hpvcfs1.HP.COM> <40889@mips.mips.COM>
Sender: jackk@shasta.Stanford.EDU (Jack Kouloheris)
Reply-To: jackk@shasta.UUCP (Jack Kouloheris)
Organization: Stanford University
Lines: 39

In article <40889@mips.mips.COM> keith@mips.COM (Keith Garrett) writes:
>In article <1080006@hpvcfs1.HP.COM> johne@hpvcfs1.HP.COM (John Eaton) writes:
>>BTW, Does anyone worry about Best Case/Worst Case analysis? Its easy to
>>anaylze a circuit if you assume that everything is at worst case but that
>>will probably never occur. What you will see is some combination of timings
>>that fall between best and worst. (Best in many cases is not even speced).
>>How do you analyze the semi-infinite number of possible timings that a typical
>>circuit can experiance?
>>
>you can't. you just look at the corners and the middle, and hope that the test
>guys have taken care of other anomalies. >

While it is not possible to individually simulate each possible case,
one can perform simulations to insure that the design is relatively 
robust with respect to timing variations. There are multiple-valued
logic simulators that propagate delay uncertainties through the logic.
(i.e. the output of a gate is shown to be in transition from
the earliest possible change to the latest possible change). If data
is ever used or clocked while it is unstable, this will show up in
the simulation. Of course, one can't run all possible simulations
either, so, as pointed outin another posting, it is also important to
run static timing analysis that propagates this sort of delay
uncertainty.  None of this guarantees that the circuit will work
but the design should be significantly more robust than one slapped
together with nominal timing. It's one thing to build 100 or 1000
working systems, quite another to build a million *and* to service them.

>fortunately, things tend to track
>(ie. longer output delays and shorter setup times tend to go together).

This tends to be true on die and to some extent across a wafer,
but in a system of several thousand chips which may come from
different wafer lots and manufacturers, there may not be any
chip to chip correlation. On chip, four corner simulation plus nominal
means a lot more than at the system level. Additionally, some circuit
simulators (ASTAP, HSPICE) provide the capability of running a 
simulation multiple times , varying the components through a specified
statistical distribution. This provides an indication of how the
output behavior of a circuit may vary with manufacturing variation.