Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!uunet!wuarchive!zaphod.mps.ohio-state.edu!usc!bbn.com!pdsmith From: pdsmith@bbn.com (Peter D. Smith) Newsgroups: comp.arch Subject: Re: Do chip timing specs mean anything? Message-ID: <58965@bbn.BBN.COM> Date: 16 Aug 90 17:38:46 GMT References: <1990Aug4.152038.1132@sbcs.sunysb.edu> <1080006@hpvcfs1.HP.COM> <40889@mips.mips.COM> Sender: news@bbn.com Reply-To: pdsmith@spca.bbn.com (Peter D. Smith) Organization: Bolt Beranek and Newman Inc., Cambridge MA Lines: 34 >In article <1080006@hpvcfs1.HP.COM> johne@hpvcfs1.HP.COM (John Eaton) writes: >>BTW, Does anyone worry about Best Case/Worst Case analysis? Its easy to >>anaylze a circuit if you assume that everything is at worst case but that >>will probably never occur. What you will see is some combination of timings >>that fall between best and worst. (Best in many cases is not even speced). >>How do you analyze the semi-infinite number of possible timings that a typical >>circuit can experiance? >> There are commercial programs that will analyze and/or simulate a circuit under varying conditions. I used to work on one such simulator, LASAR, sold by Teradyne; our competition including Verilog, HiLo from Genrad, and the simulators available from Daisy, Mentor, and Valid among others. LASAR would, given the circuit diagram, knowledge of the specific parts to be used (different processes, of course, are different parts) including the correlation of the speed of internal gates (eg, the sn74ls04d gates will always track one another to 90%), which gates go into which package, and the signals to be applied to the circuit (which could be fuzzy), tell you what happened and why -- which flip flops has timing specs violated, which buses were driven but multiple drivers, etc. It was really pretty nifty. Most of our customers were quite concerned with accuracy, and really liked the fact that we analyzed all possible cases simultaneously -- the simulator knew where the leading and trailing edges were and would compare setup and hold times against best/best, worst/worst, best/worse, and worse/best. If there was a conflict, it would trace back through the circuit to see if the two edges were correlated in some way. Peter D. Smith Disclaimer: I used to work there, I have fond memories of everyone, and I liked and respected the product.