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From: lewine@dg-rtp.dg.com (Donald Lewine)
Newsgroups: comp.arch
Subject: Re: Do chip timing specs mean anything?
Message-ID: <776@dg.dg.com>
Date: 16 Aug 90 13:02:50 GMT
References: <1990Aug4.152038.1132@sbcs.sunysb.edu> <1080006@hpvcfs1.HP.COM>
Sender: root@dg.dg.com
Reply-To: uunet!dg!lewine
Organization: Data General Corporation
Lines: 29

In article <1080006@hpvcfs1.HP.COM>, johne@hpvcfs1.HP.COM (John Eaton) writes:
|> How do you analyze the semi-infinite number of possible timings that
a typical
|> circuit can experiance?

This is not as hard as it sounds.  Many simulators and timing tools
do this today.  What they do is have 3 states Zero, Unknown, and One.
[[In practice, they may have many more states.  The idea is the same.]]

A gate goes from Zero->Unknown in the minimum delay and from 
Unknown->One in the maximum time.  With a little thought you can 
come up with all of the boolean rules for unknown (0 AND U = 0,
1 OR U = 1, 1 AND U = U, and so on).

If you ever try to clock a U into a flip-flop, you have a timing 
hazard.

NOTE:  This makes it important to have reasonable minimum delay
	   for devices.  Many vendors spec the min delay as zero.  That
	   is a real bitch.

--
--------------------------------------------------------------------
Donald A. Lewine				(508) 870-9008
Data General Corporation		(508) 366-0750
4400 Computer Drive. MS D112A
Westboro, MA 01580  U.S.A.

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