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From: gsteckel@vergil.East.Sun.COM (Geoff Steckel - Sun BOS Software)
Newsgroups: sci.electronics
Subject: Re: chips into powered sockets
Message-ID: <2398@east.East.Sun.COM>
Date: 14 Aug 90 17:02:28 GMT
References: <23655@dartvax.Dartmouth.EDU>
Sender: news@east.East.Sun.COM
Reply-To: gsteckel@east.sun.com (Geoff Steckel - Sun BOS Software)
Distribution: sci.electronics
Organization: Omnivore Technology, Newton, Mass. (617)969-3448
Lines: 49

In article <23655@dartvax.Dartmouth.EDU> charles.hitchcock@dartmouth.edu (Charlie Hitchcock) writes:
>
>I have come to believe that plugging in a (CMOS) chip
>into a powered socket can potentially damage the chip.
>After all, doesn't AT&T use special technology to let
>them hot-swap a board in a telephone switching system?
>
>Now that I have an application where I want to insert
>and remove a chip into/from a powered socket, I am hard-
>pressed to explain what electrical phenomena would occur
>that could do damage.
>
>Is hot-swapping a chip a bad idea?  Why?  What do
>commercial chip test systems do?

Those expert in the art please correct details...

There are several possible results of plugging a chip into a "hot" socket,
mostly as a result of connecting Vee (ground) and I/O before Vcc (+5):
(I've destroyed chips in all these fashions).

1) Mostly a problem for bipolar chips:  if an input and ground are connected
before VCC, the input-to-VCC spec can be exceeded, damaging the input structure.
LSTTL is fairly immune, but naked emitter inputs of old TTL would blow easily.
I don't know about the base inputs (PNP or NPN) of some of the 74F and 74AS parts.
(I haven't tried this experiment lately!)

2) Mostly a problem for CMOS chips: if an output is raised above VCC to a low
impedance source, parasitic diodes can start sinking current.  In many CMOS
processes, one of the output transistors has a parasitic PNPN (otherwise known
as a SCR) path to the substrate.  When power is applied to VCC, this SCR is
already on, shorting the power to ground via the chip substrate.  This was and
is a problem with analog multiplexor chips where input voltages are hard to
constrain - protection circuitry that doesn't degrade normal operation is hard
to design unless the process uses dielectric isolation (expensive).
This behavior is one type of `latch-up'.

3) Not quite the same problem, but if VCC is shorted to ground (as in an
unpowered board being inserted; the decoupling caps provide a low impedance
VCC-VEE), applying a low impedance voltage source to a bipolar output can cause
(a slightly different form of) latch-up as well.

There are other problems with analog circuitry.


	geoff steckel (gwes@wjh12.harvard.EDU)
			(...!husc6!wjh12!omnivore!gws)
Disclaimer: I am not affiliated with Sun Microsystems, despite the From: line.
This posting is entirely the author's responsibility.