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From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: Re: Synchronising Clocks.
Keywords: 25MHz 20MHz CLOCK SYNC
Message-ID: <41045@mips.mips.COM>
Date: 23 Aug 90 14:16:32 GMT
References: <1990Aug22.164935.12358@cs.city.ac.uk>
Sender: news@mips.COM
Reply-To: mark@mips.COM (Mark G. Johnson)
Organization: MIPS Computer Systems, Inc.
Lines: 26

In article <1990Aug22.164935.12358@cs.city.ac.uk> matt@cs.city.ac.uk (Matthew Sillitoe) writes:
  >Problem: Need to syncronise two clocks one at 25MHz, and one at 20MHz, under
  >         the control of one TTL input. The clock needs to switched from one
  >         to the other without producing 'glithches'. The 20MHz, and 25MHz 
  >         clocks are pregenerated.

William K. Stewart, "A Solution to a Special Case of the Synchronization
Problem", IEEE Trans. Computers, 1985-6 (don't have page #'s or exact date
on my preprint).  From the Abstract: "... This paper describes a synchronizer
that exhibits an arbitrarily low failure rate and a short propagation delay
for the special case of synchronizing a signal that is synchronous with
some periodic signal."

Note the phrase "special case" in the title -- that's the key.  The authors
haven't cheated Mother Nature, they've just found an interesting and useful
subproblem (data input to be synched is *periodic*) which is tractable.
Potential flamers, read the paper...

In the paper they design *and build* *and measure* physical TTL hardware
that accepts data in from an 8MHz periodic source, and synchronizes
it with a local 10MHz clock.  Average latency is 60ns, i.e. less than one
tick of the local clock.
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086
	(408) 524-8308    mark@mips.com  {or ...!decwrl!mips!mark}