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From: stevew@wyse.wyse.com (Steve Wilson x2580 dept303)
Newsgroups: comp.arch
Subject: Re: Do chip timing specs mean anything?
Message-ID: <2865@wyse.wyse.com>
Date: 23 Aug 90 17:43:29 GMT
References: <1990Aug4.152038.1132@sbcs.sunysb.edu> <1080006@hpvcfs1.HP.COM> <40889@mips.mips.COM> <27@shasta.stanford.edu>
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Reply-To: stevew@wyse.UUCP (Steve Wilson x2580 dept303)
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In article <27@shasta.stanford.edu> jackk@shasta.UUCP (Jack Kouloheris) writes:
>it is also important to
>run static timing analysis that propagates this sort of delay
>uncertainty.  None of this guarantees that the circuit will work
>but the design should be significantly more robust than one slapped
>together with nominal timing. 
> rest of posting deleted....

I'd have to disagree with this.  A static timing analyzer that WORKS
will tell you the best case problems and the worst case  problems.
You fix em, then you've got a tight design.  Of the automated tools
I've used I've found that the static analysis tool is perhaps the
best way to solve the problem.  For this tool to work you have to
know a great deal about the circuit in question including layout
information, best and worst case numbers through each of the logic
paths in the design, and best and worst case propagation on the PCB
as well.  

Now my experience is with these tools is primarily with MSI implemenations
of processors accross multiple boards.  I'd expect the same to
be true in silicon based designs.  Any comments?

Steve Wilson