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From: cprice@mips.COM (Charlie Price)
Newsgroups: comp.arch
Subject: Re: Workstation Data Integrity
Keywords: interrupts
Message-ID: <41066@mips.mips.COM>
Date: 24 Aug 90 03:53:45 GMT
References: <1990Aug3.204358.330@portia.Stanford.EDU> <40694@mips.mips.COM> <2399@crdos1.crd.ge.COM> <1990Aug10.171744.9639@zoo.toronto.edu> <14623@drilex.UUCP> <1990Aug20.151438.27121@ecn.purdue.edu> <10307@pt.cs.cmu.edu>
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Reply-To: cprice@mips.COM (Charlie Price)
Organization: MIPS Computer Systems, Inc.
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In article <10307@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes:
>...  So, we got
>to be the people who noticed the NMI hardware bug.  Recall that the
>8088 has prefix instructions, which change the addressing of the
>following instruction.  An NMI could be honored between the two, but
>the interrupt return would "forget" the prefixing.
>
>While we're on the subject, RISC machines with branch delay slots
>have a similar problem.  Of course, the easy instruction decoding
>means that they can push some of the work into the interrupt
>handlers.  Does anyone want to describe how their favorite machine
>did this?

Here is an answer for the MIPS R2000, R3000, and R6000.

An exception causes a trap to kernel code and loads a couple registers:
EPC - Exception Program Counter - the address at which execution
      should resume.
Cause - various bits of information about the cause of the exception.
Normally, the EPC points at the instruction that caused the exception
or, in the case of interrupts, that was about to be fetched.
If an exception occurs during execution of the instruction
in a branch delay slot or "between" a branch and the
instruction in the branch-delay slot,
the Cause register has the Branch Delay (BD) bit set and the
EPC register contains the address of the branch instruction.

For interrupts, you don't generally care about this and no
special processing is required.
Only if you have to examine the instruction that caused the fault
do you have to decide whether to look at the instruction pointed
at by the EPC or the next instruction.

This isn't *quite* the whole story.
TLB misses, for instance, are special and have other hardware support
so you don't have to look at the instruction to figure out
the address that missed in the TLB.

If the kernel has to emulate the instruction in the branch delay slot
(wierd FP stuff for instance) then it can't re-execute the
branch instruction and will need to emulate it as well.
This is a rare case, so the performance is not a problem.
-- 
Charlie Price    cprice@mips.mips.com        (408) 720-1700
MIPS Computer Systems / 928 Arques Ave. / Sunnyvale, CA   94086-23650