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From: jkenton@pinocchio.encore.com (Jeff Kenton)
Newsgroups: comp.arch
Subject: Re: Workstation Data Integrity
Message-ID: <12578@encore.Com>
Date: 24 Aug 90 15:05:14 GMT
References: <10307@pt.cs.cmu.edu>
Sender: news@encore.Com
Lines: 24

From article <10307@pt.cs.cmu.edu>, by lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay):
> 
>                         An NMI could be honored between the two, but
> the interrupt return would "forget" the prefixing.
> 
> While we're on the subject, RISC machines with branch delay slots
> have a similar problem.  Of course, the easy instruction decoding
> means that they can push some of the work into the interrupt
> handlers.  Does anyone want to describe how their favorite machine
> did this?

On the 88000 (my current favorite machine) the instruction pipeline has
three stages -- XIP, NIP, FIP.  These tell you where you've been, where
you are and where you're going.  Restoring the proper values gets you
back exactly where you are supposed to be.  Not really trouble.

The only problem to beware of is single stepping or other debugging, where
you may be looking at a program interrupted at a delay slot.  In this case
"go (or step) from the pc" can be ambiguous.

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      jeff kenton  ---	temporarily at jkenton@pinocchio.encore.com	 
		   ---  always at (617) 894-4508  ---
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