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From: hawkes@mips.COM (John Hawkes)
Newsgroups: comp.arch
Subject: Re: 64 bits for times....
Message-ID: <41074@mips.mips.COM>
Date: 24 Aug 90 17:15:54 GMT
References: <5539@darkstar.ucsc.edu> <13285@yunexus.YorkU.CA> <30728@super.ORG> <26012@bellcore.bellcore.com> <11187@alice.UUCP> <1990Aug23.022416.14798@sco.COM> <703@exodus.Eng.Sun.COM> <32015@super.ORG>
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Reply-To: hawkes@mips.COM (John Hawkes)
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In article <32015@super.ORG> rminnich@udel.edu (Ronald G Minnich) writes:
>In article <703@exodus.Eng.Sun.COM>, rtrauben@cortex.Eng.Sun.COM
>(Richard Trauben) writes:
>|> >       ld.l    r1, CLOCK
>|> >       <instr>
>|> >       ld.l    r2, CLOCK
>|> You just measured the execution time sum of TWO instructions:
>|> <instr> PLUS <ld> execution time where the <ld> includes bus 
>|> arbitration and memory access time to the TOD clock resource.  
>
>huh? 
>CLOCK is a fast register right there on the processor in most cases. 
>I can't imagine anyone in their right mind putting that high-res 
>clock at the other 
>end of a memory bus if it has any kind of resolution. 

Actually, there is a specific Elxsi instruction to read the clock register, and
the register lives on the ALU board (the principal board of the three boards
comprising the CPU).  I don't recall the latency, but I doubt it requires more
than one or two cycles.  The Elxsi CPI is something on the order of two or
three if instructions and data are cached.
-- 

John Hawkes
{ames,decwrl}!mips!hawkes  OR  hawkes@mips.com