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From: tim@proton.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Workstation Data Integrity
Message-ID: <1990Aug25.014235.6894@mozart.amd.com>
Date: 25 Aug 90 01:42:35 GMT
References: <1990Aug3.204358.330@portia.Stanford.EDU> <40694@mips.mips.COM> <2399@crdos1.crd.ge.COM> <1990Aug10.171744.9639@zoo.toronto.edu> <14623@drilex.UUCP> <1990Aug20.151438.27121@ecn.purdue.edu> <10307@pt.cs.cmu.edu> <41066@mips.mips.COM>
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Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc., Austin, Texas
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| In article <10307@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes:
| >...  So, we got
| >to be the people who noticed the NMI hardware bug.  Recall that the
| >8088 has prefix instructions, which change the addressing of the
| >following instruction.  An NMI could be honored between the two, but
| >the interrupt return would "forget" the prefixing.
| >
| >While we're on the subject, RISC machines with branch delay slots
| >have a similar problem.  Of course, the easy instruction decoding
| >means that they can push some of the work into the interrupt
| >handlers.  Does anyone want to describe how their favorite machine
| >did this?

The Am29000 simply uses 2 PC buffer registers to hold the return
address(es).  Normally these are sequential, but if an interrupt or
trap occurs between a branch and its delay slot, then PC1 points to
the delay instruction and PC0 points to the branch target.  The
interrupt-return (IRET) instruction uses both these addresses (if
required) to restart the instruciton stream correctly.

In article <41066@mips.mips.COM> cprice@mips.COM (Charlie Price) writes:
| Here is an answer for the MIPS R2000, R3000, and R6000.
| 
| An exception causes a trap to kernel code and loads a couple registers:
| EPC - Exception Program Counter - the address at which execution
|       should resume.
| Cause - various bits of information about the cause of the exception.
| Normally, the EPC points at the instruction that caused the exception
| or, in the case of interrupts, that was about to be fetched.
| If an exception occurs during execution of the instruction
| in a branch delay slot or "between" a branch and the
| instruction in the branch-delay slot,
| the Cause register has the Branch Delay (BD) bit set and the
| EPC register contains the address of the branch instruction.

Just curious -- what happens in the perverse case that someone tries a
conditional branch-and-link instruction using the link register as a
conditional source, i.e.:

	<r31 contains -1>
	bltzal	r31, label
				<- interrupt here
	<delay operation>

Does the link portion of the branch-and-link take place anyway,
destroying the conditional information and preventing the branch from
being restartable correctly?
	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)