Path: utzoo!dciem!array!colin
From: colin@array.UUCP (Colin Plumb)
Newsgroups: comp.arch
Subject: Re: Workstation Data Integrity
Keywords: interrupts
Message-ID: <585@array.UUCP>
Date: 24 Aug 90 20:23:59 GMT
References: <1990Aug3.204358.330@portia.Stanford.EDU> <40694@mips.mips.COM> <2399@crdos1.crd.ge.COM> <1990Aug10.171744.9639@zoo.toronto.edu> <14623@drilex.UUCP> <1990Aug20.151438.27121@ecn.purdue.edu> <10307@pt.cs.cmu.edu>
Organization: Array Systems Computing, Inc., Toronto, Ontario, CANADA
Lines: 22

In article <10307@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes:
> While we're on the subject, RISC machines with branch delay slots
> have a similar problem.  Of course, the easy instruction decoding
> means that they can push some of the work into the interrupt
> handlers.  Does anyone want to describe how their favorite machine
> did this?

The Am29000 just has two program counters, current and next.  (it
provides a previous, as well, but doesn't need it).  Most faults leave
the processor ready to continue with the next instruction; if you want
to retry instead of emulating (e.g. data TLB miss), you have to back up
the PC's a cycle.

Excpetions: instruction-fetch errors (TLB miss, protection violation, etc.),
illegal opcode (as opposed to software traps) and protection violation
(a supervisor-only instruction).   These retry the current instruction.
I don't think there's any deep reason, it was just easier to do that way
because it's detected during decode.  To skip one of these instructions,
you just point the current PC at a NOP somewhere and leave the next PC
alone.
-- 
	-Colin