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From: chris@mimsy.umd.edu (Chris Torek)
Newsgroups: comp.arch
Subject: MIPS R[236]000 interrupts (was Workstation Data Integrity)
Message-ID: <26200@mimsy.umd.edu>
Date: 25 Aug 90 05:10:03 GMT
References: <1990Aug3.204358.330@portia.Stanford.EDU> <40694@mips.mips.COM> <1990Aug25.014235.6894@mozart.amd.com>
Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742
Lines: 24

>In article <41066@mips.mips.COM> cprice@mips.COM (Charlie Price) writes:
>>If an exception occurs during execution of the instruction in a branch
>>delay slot or "between" a branch and the instruction in the branch-
>>delay slot, the Cause register has the Branch Delay (BD) bit set and the
>>EPC register contains the address of the branch instruction.

[and the interrupt handling routine has to emulate the branch]

In article <1990Aug25.014235.6894@mozart.amd.com> tim@proton.amd.com
(Tim Olson) writes:
>Just curious -- what happens in the perverse case that someone tries a
>conditional branch-and-link instruction using the link register as a
>conditional source ...

There are a number of things you *can* do which are effectively labelled
`unpredictable'; this is one of them.  If you try it your code misbehaves.
(The machine continues to function normally, but your program mysteriously
bombs sometimes.)

(Surely the 29000 has some places where the architecture book says `if
you do this, you lose'?)
-- 
In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 405 2750)
Domain:	chris@cs.umd.edu	Path:	uunet!mimsy!chris