Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!lll-winken!llnl!physics.llnl.gov
From: brooks@physics.llnl.gov (Eugene D. Brooks III)
Newsgroups: comp.arch
Subject: Killer Micro II
Message-ID: <527@llnl.LLNL.GOV>
Date: 25 Aug 90 12:57:44 GMT
Sender: news@llnl.LLNL.GOV
Organization: Lawrence Livermore National Laboratory
Lines: 36

Just when you were beginning to think that it was safe to enter
the computer market again, meaner critters come crawling out
at the IEEE sponsored Hot Chips Symposium, in Santa Clara.

As is well known to the readers of this group, there has been
a lot of discussion with regard to whether or not the Killer Micros
will supplant supercomputers.  The Killer Micros have been posting
incredible performances for scalar codes, clearly documented in the
LANL report comparing the IBM RS/6000 running at 30 MHZ to the YMP.
Many participants in this group, highlited by one recent conversion
to killer micros on the basis of productivity issues, have argued that the
Killer Micros will not supplant traditional vector processing supercomputers
until they provide equally high vector performance.  Just in case the
argument is valid, the Killer Micros are dealing with the issue...

Meet Killer Micro II, described by Bipolar Integrated Technology, of Portland
Oregon, at the Hot Chips Symposium which was held in Santa Clara this month:

-> 200K transistors on single ECL chip which dissapates 28 watts

-> Clocked at 100 MHZ (80 MHZ Cray 1, 117 MHZ XMP, 154 MHZ YMP)

-> Two 64 bit read ports, one 64 write port, concurrent transfers

-> Capable of one 64 bit ADD and one 64 bit MULT each clock
	IEEE DIVIDE, SQRT tossed in for free

-> Full Integer ALU operations

-> 200 MFLOPS, sustainable, peak performance

Read, Read, FLOP, FLOP, Write: each and every clock!


Anyone got some ``vector register'' chips, and decent memory chips,
to keep this beast fed???